1. Field of the Invention
The present invention relates generally to I/O (input/output) transceiver circuits and more specifically to GTL (Gunning Transceiver Logic) I/O transceivers having a pulsed latch receiver circuit.
2. Art Background
High performance VLSI processors having several hundred I/O lines and associated transceiver circuits are common. Wide (e.g. 64 bit), high-speed I/O busses are used to interconnect VLSI components. The VLSI components use I/O transceiver circuits to drive information on and receive information from the I/O bus. Various I/O transceiver circuits are known. Examples are CMOS (Complementary Metal-Oxide Semiconductor), ECL (Emitter Coupled Logic), BTL (Backplane Transceiver Logic), and standard GTL (Gunning Transceiver Logic) transceiver circuits. Power dissipation, signal quality, noise immunity, and performance are important factors to consider when designing a transceiver circuit and I/O bus.
Conventional CMOS transceivers coupled with unterminated I/O signal busses suffer from excessive noise and ringing at the low to high transition and, therefore, do not have suitable speed performance to meet the demands of today's high-speed busses. Terminated CMOS transceivers have good speed performance, but dissipate about five times more power than standard GTL transceivers. Traditional ECL designs using terminated transmission line interconnect techniques provide high speed, but dissipate excessive power. Standard GTL transceivers use terminated signal lines and I/O signal voltage levels of approximately 0.4 V and 1.2 V to achieve high speed and a power dissipation of about 9 mW for each driver and 5.5 mW for each receiver. Standard GTL transceiver circuits are described in U.S. Pat. No. 5,023,488 issued to Gunning et al. An article related to GTL transceivers is Linley Gwennap, "Sun, Xerox to License XDBus Technology," Microprocessor Report, 8 March, 1993, pp. 1, 6, and 8.
The receiver circuit of the standard GTL transceiver utilizes a CMOS differential amplifier that dissipates constant DC current. This DC current is undesirable in a microprocessor for three reasons: 1) the DC current contributes to thermal heating of the microprocessor, 2) the DC current consumes battery power of mobile computers even when the microprocessor is put into a static mode to save power, and 3) the DC current is too large to allow IDDQ testing of the microprocessor. IDDQ testing comprises measuring the static DC current of the microprocessor to detect faulty devices on the microprocessor.
For a typical design, the receiver circuit consumes about 5.5 mW of power during normal operation. For this design, the receiver circuits of a VLSI chip having 200 I/0 pins would dissipate about 1.1 W of power during normal operation. As overall chip power dissipation increases, temperature controlling devices such as heat sinks, cooling fans, etc. are required to maintain proper microprocessor operation. Power dissipation of today's microprocessors is high enough that thermal considerations significantly affect overall computer system design.
Therefore, an I/O transceiver having a pulsed latch receiver circuit is needed.